module StateMachine(
    input   wire                        clk         ,
    input   wire                        rstn        ,
    input   wire    [WIDTH1-1:0]        insigs      ,
    output  wire    [WIDTH2-1:0]        outsigs      
);

reg [WIDTH3-1:0] state;
reg state_next;

// 状态迁移
always @(posedge clk, negedge rstn) begin 
    if(rstn == 1'b0) begin 
        state <= STATE_IDLE;
    end
    else begin 
        state <= state_next;
    end
end

// 次态逻辑
always @(*) begin 
    case(state) 
        STATE_IDLE: 
            if(insigs == INPUT1) begin 
                state_next = STATE1;
            end
            else if(insigs == INPUT2) begin 
                state_next = STATE2;
            end
            else begin 
                ...
            end
        STATE1: 
            if(insigs == INPUT1) begin 
                state_next = STATE3;
            end
            else if(insigs == INPUT2) begin 
                state_next = STATE4;
            end
            else begin 
                ...
            end
        STATE2: ...
        default: ...
    endcase
end

// 输出逻辑
always @(*) begin 
    if(rstn == 0) begin 
        outsigs = 0;
    end
    else begin 
        case(state)
            STATE_IDLE: outsigs = (insigs == INPUT1) ? OUTPUT1 : OUTPUT2;
            STATE1: ...
            ...
            default: ...
        endcase
    end
end

endmodule